Publications

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Calibration-Based Differentiable Timing Optimization in Non-linear Global Placement

Systolic Array Placement on FPGAs

The 2023 MLCAD FPGA Macro Placement Benchmark Design Suite and Contest Results

General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism

RapidStream 2.0: Automated Parallel Implementation of Latency Insensitive FPGA Designs Through Partial Reconfiguration

Global Placement Exploiting Soft 2D Regularity

FLOPS: Efficient On-Chip Learning for Optical Neural Networks Through Stochastic Zeroth-Order Optimization

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

ABCDPlace: Accelerated Batch-based Concurrent Detailed Placement on Multi-threaded CPUs and GPUs

S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity

High-Definition Routing Congestion Prediction for Large-Scale FPGAs

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

PDF Code Slides

Simultaneous Placement and Clock Tree Construction for Modern FPGAs

PDF

UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine

PDF

Placement Mitigation Techniques for Power Grid Electromigration

PDF