I am a Staff Software Engineer in the Vivado Implementation Team at Xilinx.
Prior to joining Xilinx, I received my Ph.D. degree in Electrical and Computer Engineering from the University of Texas at Austin in 2019,
supervised by Prof. David Z. Pan in the UTDA Laboratory.
I received my B.S. degree in Microelectronics from Shanghai Jiao Tong University in 2013.
I do research in Electronic Design Automation (EDA).
I like developing tools to increase the productivity of circuit designers, improve the quality of modern VLSI systems, and overcome chip design challenges.
My Ph.D. dissertation was on Placement Algorithms for Large-Scale Heterogeneous FPGAs.
I have received the Best Paper Award at DAC 2019, the Silver Medal in ACM Student Research Contest at ICCAD 2018, and the 1st-place awards in the FPGA placement contests of ISPD 2016 and 2017.
I have interned at Xilinx, Cadence, Apple, and ARM.
- 6⁄2019 : Our paper, elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs, is accepted by ICCAD’19.
- 6⁄2019 : My co-authored paper, DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement, received the Best Paper Award at DAC’19.
- 2⁄2019 : My co-authored paper, DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement, is accepted by DAC’19.
- 11⁄2018 : Our paper, Simultaneous Placement and Clock Tree Construction for Modern FPGAs, is accepted by FPGA’19.
- 11⁄2018 : I won the Silver Medal at ACM/SIGDA Student Research Competition held at the ICCAD 2018.
- 8⁄2018 : I received the George J. Heuer, Jr. Ph.D. Endowed Graduate Fellowship Fund from the Cockrell School of Engineering, UT-Austin.
- 8⁄2018 : I finished my internship at Xilinx and received the 3rd-Place Award of the intern showcase presentation.
- 7⁄2018 : Our journal paper, A New Paradigm for FPGA Placement without Explicit Packing, is accepted by TCAD.
- 6⁄2018 : My co-authored journal paper, A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion, is accepted by TCAD.
- 12⁄2017 : Our journal paper, UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine, is accepted by TODAES.