I am currently a Ph.D. candidate at the Department of Electrical and Computer Engineering, University of Texas at Austin,
working with Prof. David Z. Pan.
Prior to coming to UT, I graduated from Shanghai Jiao Tong University with B.S. in Microelectronics in 2013.
I do research in Electronic Design Automation (EDA).
I like developing tools to increase the productivity of circuit designers, improve the quality of modern VLSI systems, and overcome chip design challenges.
I have won the two 1st-place awards of ISPD 2016 and 2017 FPGA placement contests hold by Xilinx.
I have interned at Xilinx, Cadence, Apple, and ARM.
- 2⁄2019 : My co-authored paper, DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement, is accepted by DAC’19.
- 11⁄2018 : Our paper, Simultaneous Placement and Clock Tree Construction for Modern FPGAs, is accepted by FPGA’19.
- 11⁄2018 : I won the Silver Medal at ACM/SIGDA Student Research Competition held at the ICCAD 2018.
- 8⁄2018 : I received the George J. Heuer, Jr. Ph.D. Endowed Graduate Fellowship Fund from the Cockrell School of Engineering, UT-Austin.
- 8⁄2018 : I finished my internship at Xilinx and received the 3rd-Place Award of the intern showcase presentation.
- 7⁄2018 : Our journal paper, A New Paradigm for FPGA Placement without Explicit Packing, is accepted by TCAD.
- 6⁄2018 : My co-authored journal paper, A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion, is accepted by TCAD.
- 12⁄2017 : Our journal paper, UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine, is accepted by TODAES.