Journal Articles

[J3]  . UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement EngineACM Transactions on Design Automation of Electronic Systems (TODAES), 2017.  (Submitted)

[J2]  . UTPlaceF: A Routability-Driven FPGA Placer with Physical and Congestion Aware PackingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017.  (Accepted)

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[J1]  . An Optimization Procedure for Coil Design in a Dual Band Wireless Power and Data Transmission SystemECS Transactions (ECST), 2013. 

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Conference Papers

[C5]  . A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell InsertionIEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), 2018. 

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[C4]  . UTPlaceF 3.0: A Parallelization Framework for Modern FPGA Global PlacementIEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017.  (Invited Paper)

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[C3]  . Placement Mitigation Techniques for Power Grid ElectromigrationIEEE International Symposium on Low Power Electronics and Design (ISLPED), 2017. 

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[C2]  . UTPlaceF: A Routability-Driven FPGA Placer with Physical and Congestion Aware PackingIEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2016.  (Invited Paper, 1st-Place Award of ISPD 2016 Contest)

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[C1]  . Live demonstration: An Optimization Software and a Design Case of a Novel Dual Band Wireless Power and Data Transmission SystemIEEE International Symposium on Circuits and Systems (ISCAS), 2014. 

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