News

• ²⁄₂₀₂₀ : My co-authored paper, FLOPS: Efficient On-Chip Learning for Optical Neural Networks Through Stochastic Zeroth-Order Optimization, is accepted by DAC’20.
• ¹⁄₂₀₂₀ : My co-authored paper, ABCDPlace: Accelerated Batch-based Concurrent Detailed Placement on Multi-threaded CPUs and GPUs, is accepted by TCAD.
• ⁸⁄₂₀₁₉ : My co-authored paper, High-Definition Routing Congestion Prediction for Large-Scale FPGAs, is accepted by ASPDAC’20.
• ⁸⁄₂₀₁₉ : My co-authored paper, S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity, is accepted by ASPDAC’20.
• ⁶⁄₂₀₁₉ : Our paper, elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs, is accepted by ICCAD’19.
• ⁶⁄₂₀₁₉ : My co-authored paper, DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement, received the Best Paper Award at DAC’19.
• ²⁄₂₀₁₉ : My co-authored paper, DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement, is accepted by DAC’19.
• ¹¹⁄₂₀₁₈ : Our paper, Simultaneous Placement and Clock Tree Construction for Modern FPGAs, is accepted by FPGA’19.
• ¹¹⁄₂₀₁₈ : I won the Silver Medal at ACM/SIGDA Student Research Competition held at the ICCAD 2018.
• ⁸⁄₂₀₁₈ : I received the George J. Heuer, Jr. Ph.D. Endowed Graduate Fellowship Fund from the Cockrell School of Engineering, UT-Austin.
• ⁸⁄₂₀₁₈ : I finished my internship at Xilinx and received the 3rd-Place Award of the intern showcase presentation.
• ⁷⁄₂₀₁₈ : Our journal paper, A New Paradigm for FPGA Placement without Explicit Packing, is accepted by TCAD.
• ⁶⁄₂₀₁₈ : My co-authored journal paper, A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion, is accepted by TCAD.
• ¹²⁄₂₀₁₇ : Our journal paper, UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine, is accepted by TODAES.